1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register for use as a scanning-line driving circuit for an image display apparatus or the like, which is formed by field effect transistors of the same conductivity type only.
2. Description of the Background Art
An image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display includes a display panel in which a plurality of pixels are arrayed in a matrix. A gate line (scanning line) is provided for each row of pixels (pixel line), and gate lines are sequentially selected and driven in a cycle of one horizontal period of a display signal, so that a displayed image is updated. As a gate-line driving circuit (scanning-line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register for performing a shift operation in one frame period of a display signal can be used.
To reduce the number of steps in the manufacturing process of a display apparatus, such shift register used as the gate-line driving circuit is preferably formed by field effect transistors of the same conductivity type only. Accordingly, various types of shift registers formed by N- or P-type field effect transistors only and display apparatuses containing such shift registers have been proposed (e.g., Japanese Patent Application Laid-Open Nos. 2004-246358 and 2004-103226). As a field effect transistor, a metal oxide semiconductor (MOS) transistor, a thin film transistor (TFT), or the like is used.
A typical shift register shown in, e.g., FIG. 7 of JP2004-246358 includes, in the output stage, a first transistor (pull-up MOS transistor Q1) connected between an output terminal (first gate-voltage signal terminal GOUT in JP2004-246358) and a clock terminal (first power clock CKV) and a second transistor (pull-down MOS transistor Q2) connected between the output terminal and a reference voltage terminal (gate-off voltage terminal VOFF). A clock signal input to the clock terminal is transmitted to the output terminal with the first transistor turned on and the second transistor turned off, so that the shift register outputs an output signal.
Particularly, each of shift registers constituting a gate-line driving circuit needs to activate each gate line by charging at high speeds using the output signal, which requires the first transistor to have a high driving capability (current driving capability). Accordingly, a gate-source voltage of the first transistor is preferably maintained high even while the output terminal, i.e., the source of the first transistor is at the H (high) level. Therefore, the shift register disclosed in JP2004-246358 is provided with a step-up capacitor (capacitor C) between the gate and source of the first transistor, and is configured such that the gate of the first transistor is also stepped up when the output terminal rises to the H level.
As the degree of step-up increases, the gate-source voltage of the first transistor increases, which in turn increases the driving capability of the first transistor. Conversely, the first transistor needs to be stepped up higher in order that the shift register can charge the gate line at high speeds.